Server class computer products are constructed by the combination of modular sets of computer components. These components can consist of a number of processors, a global-shared memory environment, main memory, PCI (Peripheral Components Interface) controllers and other components as required. Server class computer products can also be configured using basic building blocks. Example building blocks include a cell, a crossbar system, a routing chip and a PCI-based input/output (I/O) subsystem. In this case, a cell consists of shared multiprocessor (SMP) system containing from one to four (or more) processors, a portion of system memory and a connection to an I/O subsystem. Normally the cell is designed such that the hardware will not limit the mixture of different types of cells within the system. Cells can also be added or removed while the system is running. In typical systems, the cell resides on a single PC board.
The components included in the system can communicate with each other through a common bus or through point-to-point communication. Point-to-point communications consist of a discrete path such as a dedicated or switched line from one system component to a second system component. In addition or as an alternative to individual point-to-point communications, a crossbar system, a second building block, can provide switched non-blocking point-to-point interconnection between a number of cells and their associated memory. In systems, the crossbars are expected to reside oh backplanes. The third basic building block, the routing chip, connects the crossbar system to a high speed link for connecting a number of nodes into a single large system. The routing chip forms a high availability firewall to prevent failures in one node from affecting other nodes. Links can also be added or removed while the system is running. The fourth basic building block, the I/O subsystem provides connections for a number of PCI buses. Each cell has a link to a single I/O subsystem which can be located in another cabinet. PCI cards or entire I/O subsystems can be added or removed while the system is running.
A node is comprised of a set of cells connected by crossbars. Node-to-node connections are made using an interfacing routing chip (RC) and associated cables. Nodes can also be connected to each other to form larger systems.
When the system architecture is fixed, individual processors within cells can be made aware of other elements in the system through an available hardware architecture map. This hardware architecture map can be provided to the processor through its inclusion in read only memory (ROM). In this configuration a processor accesses the hardware architecture map stored in ROM to determine which other system components are available and communicates accordingly.
If all the system components are connected to a common bus, a processor on the bus has access to addresses of other system components through bus converters. By traversing the bus, the processor is connected to bus converters which connect to other buses in the system. Using this information, a processor can construct a network architecture or topology which identifies other system components within the system. Within this system, when one processor addresses a message to a second processor, the bus converter and the bus become transparent and the messages are passed from the sending processor to the receiving processor. That is, there is no indication or information provided about message routing. Through the use of this network architecture or topology the processor is aware of the functional connections between system components. However, using this system the processor is unaware of the physical layout of other system components or of the overall connecting and messaging network topology.
A processor""s knowledge of the topology is important to reduce overhead associated with interactions between system components. By reducing the pathways between cooperating system components, associated overhead expenses are reduced.
Identifying the topology in a point-to-point system is more difficult then when system components are connected with a common bus. One method of identifying the topology is an exhaustive search. In an exhaustive search a single processor determines other system components by sending messages to every possible address.
Alternatively, sideband signals can be used to identify connected system components. For example, if system components have six-bit addresses, six physical wires can be run from one processor to its neighboring hardware component. The processor can then put its six-bit address on these dedicated wires and the attached physical component can determine the processor""s address through these wires. Additionally, six separate wires would have to be run from the hardware component to the processor so the processor could determine the hardware component""s six-bit address over these six dedicated wires. In this configuration accommodating 64 component addresses, twelve (12) wires are required between each set of two components so that each component would be aware of its neighboring hardware component""s address. These hardware addresses could be determined through the use of dip switches. Although this is the simplest way of passing address elements between components, it is also the most expensive in terms of wires run. In this case, software would not be required to pass component addresses since the physical wires themselves contain the addresses.
The number of wires could be reduced by the introduction of logic to serialize the exchange of address information. If a bidirectional wire is used between the two system components, a single wire can be used to exchange addresses between the two components. In this case coordination must be obtained through software or hardware components to ensure the bi-directional communication is satisfactorily obtained. However, with a bi-directional connection, sideband signals indicating neighboring components are not normally passed between the components.
Accordingly, a need exists for systems in which components can exchange address information while minimizing costs in terms of wire runs and software or hardware control components. A further need exists for a system that allows system components to generate and maintain a functional and physical topology of system components.
These and other objects, features and technical advantages are achieved by a system and method which, according to one aspect of the invention, include a method of mapping a network topology in a network that includes a plurality of nodes communicating with each other over dedicated links connecting pairs of the nodes. The method includes exchanging respective network identification information between adjacent pairs of nodes and, establishing communications with another of the nodes (i.e., the neighbor""s neighbor node) using the network identification information. Network identification information of the other node from that node, using the network identification information to establish communications with other nodes, obtaining additional network identification information from those other nodes, repeating these steps until network identification information is obtained from all of the nodes of the network and using this information determine the network topology.
According to a feature of the invention, the network identification of immediately adjacent nodes (i.e., neighboring nodes) are stored in respective network identification registers. The nodes include both terminal nodes (i.e., data users and sources) and switching nodes (i.e., communications resources). Thus, the terminal nodes include processing cells and the switching nodes may include crossbar switching devices.
According to features of the invention, the steps of identifying and recording the identification information of neighbors may be performed either iteratively (e.g., by depth first probing to reconnect topology starting outward and progressing toward a rest node).
For either cases the resultant network topology is stored by at least one of the nodes.
According to another feature of the invention the network information obtained includes both network address and device identification information.
According to another aspect of the invention, a data processing system includes a plurality of terminal nodes, each of which has a communication port and where each terminal node is assigned a unique network identification and a network identification register. A number of switching nodes are also each assigned a unique network identification, each switching node having at least two communications ports in communication combinations of (i) the other switching nodes and (ii) the terminal nodes. Network identification registers associated with each of the at least two communications ports are indexed as part of each switching node. Logic circuitry in the form of hardware or a combination of hardware, firmware and/or software, initiates an exchange of the network identification between connected terminals and switching nodes where each of the nodes stores the network identification of adjacent (i.e., neighboring) nodes in its network identification registers. A memory stores a topology of the data processing system based on the exchange of the network identification exchanged between the nodes.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described. hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.